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SC18IS600/601
SPI to I2C-bus interface
Rev. 05 -- 28 July 2008 Product data sheet
1. General description
The SC18IS600/601 is designed to serve as an interface between the standard SPI of a host (microcontroller, microprocessor, chip set, etc.) and the serial I2C-bus. This allows the host to communicate directly with other I2C-bus devices. The SC18IS600/601 can operate as an I2C-bus master-transmitter or master-receiver. The SC18IS600/601 controls all the I2C-bus specific sequences, protocol, arbitration and timing. The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source: internal (SC18IS600) versus external (SC18IS601).
2. Features
I I I I I I I SPI slave interface SPI Mode 3 Master I2C-bus controller General Purpose Input/Output (GPIO) pins: 4 (SC18IS600); 3 (SC18IS601) Two quasi-bidirectional I/O pins 5 V tolerant I/O pins High-speed SPI: N Up to 3 Mbit/s (SC18IS601) N Up to 1.2 Mbit/s (SC18IS600) High-speed I2C-bus: 400 kbit/s 96-byte transmit buffer 96-byte receive buffer 2.4 V to 3.6 V operation Power-down mode with WAKEUP pin Oscillator: internal (SC18IS600); external (SC18IS601) Active LOW interrupt output Available in very small TSSOP16 and HVQFN24 packages
I I I I I I I I
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SC18IS600/601
SPI to I2C-bus interface
3. Ordering information
Table 1. Ordering information Package Name SC18IS600IPW SC18IS601IPW SC18IS600IBS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; SOT616-3 body 4 x 4 x 0.85 mm TSSOP16 Description plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT403-1 Type number
4. Block diagram
SC18IS600
CONTROL LOGIC
RESET
INTERCONNECT BUS LINES AND CONTROL SIGNALS
MISO MOSI SCLK CS
SPI
BUFFER
I2C-BUS CONTROLLER
SDA SCL
INT
INTERRUPT CONTROL LOGIC
GENERAL PURPOSE I/Os
GPIO0 GPIO1 GPIO2 GPIO3 IO5 IO4/WAKEUP
OSCILLATOR
ON-CHIP RC OSCILLATOR
002aab712
Fig 1.
Block diagram of SC18IS600
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SC18IS600/601
SPI to I2C-bus interface
SC18IS601
CONTROL LOGIC
RESET
INTERCONNECT BUS LINES AND CONTROL SIGNALS
MISO MOSI SCLK CS
SPI
BUFFER
I2C-BUS CONTROLLER
SDA SCL
INT
INTERRUPT CONTROL LOGIC
GENERAL PURPOSE I/Os
GPIO0 GPIO1 GPIO2 IO5 IO4/WAKEUP
external clock input (CLKIN)
OSCILLATOR
002aab784
Fig 2.
Block diagram of SC18IS601
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SPI to I2C-bus interface
5. Pinning information
5.1 Pinning
GPIO0 CS RESET VSS MISO MOSI SDA SCL
1 2 3 4 5 6 7 8
002aab713
16 IO5 15 WAKEUP/IO4 14 INT 13 GPIO3 12 VDD 11 SCLK 10 GPIO2 9 GPIO1
GPIO0 CS RESET VSS MISO MOSI SDA SCL
1 2 3 4 5 6 7 8
002aab714
16 IO5 15 WAKEUP/IO4 14 INT 13 CLKIN 12 VDD 11 SCLK 10 GPIO2 9 GPIO1
SC18IS600IPW
SC18IS601IPW
Fig 3.
SC18IS600 pin configuration for TSSOP16
23 GPIO0
Fig 4.
SC18IS601 pin configuration for TSSOP16
24 n.c.
22 n.c.
21 n.c.
20 IO5
terminal 1 index area CS RESET VSS MISO MOSI SDA 1 2 3 4 5 6
19 n.c. 18 WAKEUP/IO4 17 INT 16 GPIO3 15 VDD 14 SCLK 13 GPIO2 n.c. 12
002aad707
SC18IS600IBS
n.c. 10
Transparent top view
Fig 5.
SC18IS600 pin configuration for HVQFN24
SC18IS600_601_5
GPIO1 11
7
8 SCL
n.c.
n.c.
9
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SC18IS600/601
SPI to I2C-bus interface
5.2 Pin description
Table 2. Symbol Pin description Pin TSSOP16 SC18IS600 GPIO0 CS RESET 1 2 3 1 2 3 HVQFN24 SC18IS601 SC18IS600 23 1 2 I/O I I programmable I/O pin Chip select. When CS is LOW, the SC18IS600/601 is selected. Master Reset. When active (LOW), RESET sets internal registers to the default values, and resets the I2C-bus and SPI hardware. See Table 3. ground supply voltage SPI slave data output SPI slave data input I2C-bus serial data input/output I2C-bus serial clock output programmable I/O pin programmable I/O pin SPI clock input 2.4 V to 3.6 V supply voltage programmable I/O pin external clock input Interrupt. When active (LOW), INT informs the CPU that the SC18IS600/601 has an interrupt to be serviced. INT is reset (deactivated) either when the I2CStat register is read or as a result of a master reset (RESET). This pin is an open-drain pin. WAKEUP/IO4 15 15 18 I/O Wake up the SC18IS600/601 from the Power-down mode. Pulled LOW by the host to wake-up from low power state. This pin can also be used as a quasi-bidirectional I/O when not in a power-down state. quasi-bidirectional I/O pin not connected Type Description
VSS MISO MOSI SDA SCL GPIO1 GPIO2 SCLK VDD GPIO3 CLKIN INT
4 5 6 7 8 9 10 11 12 13 14
4 5 6 7 8 9 10 11 12 13 14
3[1] 4 5 6 8 11 13 14 15 16 17
I O I I/O O I/O I/O I I I/O I O
IO5 n.c.
16 -
16 -
20
I/O
7, 9, 10, 12, 19, 21, 22, 24
[1]
HVQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
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SC18IS600/601
SPI to I2C-bus interface
6. Functional description
The SC18IS600/601 acts as a bridge between a SPI interface and an I2C-bus. It allows a SPI master device to communicate with I2C-bus slave devices. The SPI interface supports Mode 3 of the SPI specification and can operate up to 3 Mbit/s (SC18IS601).
6.1 Internal registers
The SC18IS600/601 provides internal registers for monitoring and control. These registers are shown in Table 3. Register functions are more fully described in the following paragraphs.
Table 3. Internal registers summary Bit 7 Bit 6 Bit 5 Bit 4 IO2.0 GPIO4 CR4 TO3 1 ADR4 Bit 3 IO1.1 GPIO3[2] CR3 TO2 ADR3 Bit 2 IO1.0 GPIO2 CR2 TO1 ADR2 Bit 1 IO0.1 GPIO1 CR1 TO0 ADR1 Bit 0 IO0.0 GPIO0 CR0 TE X R/W R/W R/W R/W R/W R/W Default value 0x00 0x3F 0x19 0xFE 0xF0 0x00
Register Register address 0x00 0x01 0x02 0x03 0x04 0x05
[1] [2]
IOConfig IOState I2CClock I2CTO I2CStat I2CAdr
IO3.1[1] IO3.0[1] IO2.1 0 CR7 TO6 1 ADR7 0 CR6 TO5 1 ADR6 GPIO5 CR5 TO4 1 ADR5
I2CSTAT3 I2CSTAT2 I2CSTAT1 I2CSTAT0 R
For SC18IS601, these bits are `Don't care'. For SC18IS601 GPIO3 is not used.
6.2 Register descriptions
6.2.1 Programmable IO port configuration register (IOConfig)
Pins GPIO0 to GPIO3 may be configured by software to one of four types. These are: quasi-bidirectional, push-pull, open-drain, and input-only. Two configuration bits per pin, located in the IOConfig register, select the IO type for each pin. Each pin has Schmitt-triggered input that also has a glitch suppression circuit. IO4 and IO5 are quasi-bidirectional pins and are not user-configurable. For SC18IS601, GPIO3 is non-existent. Table 4 shows the configurations for the programmable I/O pins. IOx.1 and IOx.0 correspond to GPIOx.
Table 4. IOx.1 0 0 1 1 Pin configurations IOx.0 0 1 0 1 Pin configuration quasi-bidirectional output configuration input-only configuration push-pull output configuration open-drain output configuration
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SPI to I2C-bus interface
6.2.1.1
Quasi-bidirectional output configuration Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the pin. This is possible because when the pin outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes. One of these pull-ups, called the `very weak' pull-up, is turned on whenever the pin latch for the pin contains a logic 1. This very weak pull-up sources a very small current that will pull the pin HIGH if it is left floating. A second pull-up, called the `weak' pull-up, is turned on when the pin latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled LOW by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin LOW under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the pin below its input threshold voltage. The third pull-up is referred to as the `strong' pull-up. This pull-up is used to speed up LOW-to-HIGH transitions on a quasi-bidirectional pin when the pin latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two system clock cycles quickly pulling the pin HIGH. The quasi-bidirectional pin configuration is shown in Figure 6. Although the SC18IS600/601 is a 3 V device, most of the pins are 5 V tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to VDD causing extra power consumption. Therefore, applying 5 V to pins configured in quasi-bidirectional mode is discouraged. A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression circuit.
2 SYSTEM CLOCK CYCLES
VDD P strong P very weak P weak
GPIOn, IOn pin pin latch data VSS input data glitch rejection
002aab882
Fig 6.
Quasi-bidirectional output configuration
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SPI to I2C-bus interface
6.2.1.2
Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the pin when the pin latch contains a logic 0. To be used as a logic output, a pin configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode. The open-drain pin configuration is shown in Figure 7. An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.
GPIO pin pin latch data VSS input data glitch rejection
002aab883
Fig 7.
Open-drain output configuration
6.2.1.3
Input-only configuration The input-only pin configuration is shown in Figure 8. It is a Schmitt-triggered input that also has a glitch suppression circuit.
input data glitch rejection
GPIO pin
002aab884
Fig 8.
Input-only configuration
6.2.1.4
Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the pin latch contains a logic 1. The push-pull mode may be used when more source current is needed from a pin output. The push-pull pin configuration is shown in Figure 9. A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.
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SC18IS600/601
SPI to I2C-bus interface
VDD P strong
GPIO pin N pin latch data VSS input data glitch rejection
002aab885
Fig 9.
Push-pull output configuration
6.2.2 I/O pins state register (IOState)
When read, this register returns the actual state of all programmable and quasi-bidirectional I/O pins. When written, each register bit will be transferred to the corresponding I/O pin programmed as output.
Table 5. Bit 7:6 5 4 3 2 1 0 IOState - I/O pins state register (address 0x01) bit description Symbol IO5 IO4 GPIO3 (SC18IS600 only) GPIO2 GPIO1 GPIO0 Description reserved Set the logic level on the output pins. Write to this register: logic 0 = set output pin to zero logic 1 = set output pin to one A read from this register returns states of all pins.
6.2.3 I2C-bus address register (I2CAdr)
The contents of the register represents the device's own I2C-bus address. The most significant bit corresponds to the first bit received from the I2C-bus after a START condition. The least significant bit is not used, but should be programmed with a `0'. I2CAdr is not needed for device operation, but should be configured so that its address does not conflict with an I2C-bus device address used by the bus master.
6.2.4 I2C-bus clock rates register (I2CClk)
This register determines the I2C-bus clock frequency. Various clock rates are shown in Table 6 for the SC18IS600. The frequency can be determined using Equation 1: 7.3728 x 10 2 I C-bus clock frequency = ------------------------------ ( Hz ) 4 x I 2CClk
6
(1)
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SC18IS600/601
SPI to I2C-bus interface
The I2C-bus clock frequency for the SC18IS601 can be determined using Equation 2: CLKIN 2 I C-bus clock frequency = ---------------------------- ( Hz ) 4 x I 2CClk
Table 6. I2C-bus clock frequency example at 7.3728 MHz I2C-bus clock frequency 369 kHz 263 kHz 204 kHz 97 kHz 7.2 kHz
(2)
I2CClk (decimal) 5 (minimum) 7 9 19 255 (maximum)
6.2.5 I2C-bus time-out register (I2CTO)
The time-out register is used to determine the maximum time that the I2C-bus master is allowed to complete a transfer before setting an I2C-bus time-out interrupt.
Table 7. Bit 7:1 0 I2CTO - I2C-bus time-out register (address 0x04) bit description Symbol TO[7:1] TE Description Time-out value Enable/disable time-out function logic 0 = disable logic 1 = enable
The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1 will enable the time-out function. On the SC18IS600 the time-out oscillator operates at 57.6 kHz. For the SC18IS601 the time-out oscillator frequency can be determined using Equation 3: CLKIN Time-out oscillator frequency = ------------------ ( Hz ) 128 This oscillator is fed into a 16-bit down counter. The down counter's lower nine bits are loaded with `1', while the upper seven bits are loaded with the contents of I2CTO. (3)
57.6 kHz OSCILLATOR
16-BIT DOWN COUNTER [I2CTO][111111111]
002aab715
time-out
Fig 10. Time-out value
The time-out value is an approximate value. In the case of arbitration loss, the SC18IS600/601 will transmit a START condition when the bus becomes free unless the time-out condition is reached. If the time-out condition is reached, an interrupt will be generated on the INT pin. The `I2C-bus time-out' status can be read in I2CStat.
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SPI to I2C-bus interface
6.2.6 I2C-bus status register (I2CStat)
This register reports the results of I2C-bus transmit and receive transaction between SC18IS600/601 and an I2C-bus slave device.
Table 8. Register value 0xF0 I2C-bus status Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 I2C-bus status description Transmission successful. The SC18IS600/601 has successfully completed an I2C-bus read or write transaction. An interrupt is generated on INT. This is also the default status after reset. No interrupt is generated after reset. I2C-bus device address not acknowledged. No I2C-bus slave device has acknowledged the slave address that has been sent out in an I2C-bus read or write transaction. An interrupt is generated on INT. I2C-bus device address not acknowledged. An I2C-bus slave has not acknowledged the byte that has just been transmitted by the SC18IS600/601. An interrupt is generated on INT. I2C-bus busy. The SC18IS600/601 is busy performing an I2C-bus transaction, no new transaction should be initiated by the host. No interrupt is generated. I2C-bus time-out (see Section 6.2.5 "I2C-bus time-out register (I2CTO)"). The SC18IS600/601 has started an I2C-bus transaction that has taken longer than the time programmed in I2CTO register. This could happen after a period of unsuccessful arbitration or when an I2C-bus slave is (continuously) pulling the SCL clock LOW. An interrupt is generated on INT.) I2C-bus invalid data count. The number of bytes specified in a read or write command to the SC18IS600/601. An interrupt is generated on INT.
0xF1
1
1
1
1
0
0
0
1
0xF2
1
1
1
1
0
0
1
0
0xF3
1
1
1
1
0
0
1
1
0xF8
1
1
1
1
1
0
0
0
0xF9
1
1
1
1
1
0
0
1
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SC18IS600/601
SPI to I2C-bus interface
6.3 External clock input (SC18IS601)
In this device, the processor clock is derived from an external source driving the CLKIN pin. The clock rate may be from 0 Hz up to 18 MHz.
6.4 I2C-bus serial interface
I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:
* Bidirectional data transfer between masters and slaves * Multi-master bus (no central master) * Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
* Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
* Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
* The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 11. The SC18IS600/601 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz. (Refer to UM10204, "I2C-bus specification and user manual".)
VDD
RPU RPU
I2C-bus I2C-BUS DEVICE I2C-BUS DEVICE
SDA SCL
SC18IS600/601
002aab716
Fig 11. I2C-bus configuration
6.5 Serial Peripheral Interface (SPI)
The host communicates with the SC18IS600/601 via the SPI interface. The SC18IS600/601 operates in Slave mode up to 3 Mbit/s. The SPI interface has four pins: SCLK, MOSI, MISO, and CS.
* SCLK, MOSI and MISO are typically tied together between two or more SPI devices.
Data flows from the master to the SC18IS600/601 on the MOSI (Master Out Slave In) pin and flows from SC18IS600/601 to the master on the MISO (Master In Slave Out) pin. The SCLK signal is an input to the SC18IS600/601.
* CS is the slave select pin. In a typical configuration, an SPI master selects one SPI
device as the current slave. An SPI slave device uses its CS pin to determine whether it is selected. The CS pin may be tied LOW if it is the only device on the bus. Typical connections are shown in Figure 12.
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SC18IS600/601
SPI to I2C-bus interface
master MISO MOSI SPICLK PORT
slave
SC18IS600/601
SCLK CS
slave OTHER SPI DEVICE
SCLK PORT CS
002aab717
Fig 12. SPI single master multiple slaves configuration
6.6 SPI message format
6.6.1 Write N bytes to I2C-bus slave device
SPI host sends 0x00 COMMAND NUMBER OF BYTES SLAVE ADDRESS +W DATA BYTE 1 DATA BYTE N
CS SCLK
MOSI
command 0x00
number of bytes D[7:0]
slave address A[7:1] 0
data byte 1
data byte N
002aab718
Fig 13. Write N bytes to I2C-bus slave device
The SPI host issues the write command by sending a 0x00 command followed by the total number of bytes (maximum 96 bytes excluding the address) to send and an I2C-bus slave device address followed by I2C-bus data bytes, beginning with the first byte (data byte 1) and ending with the last byte (data byte N). Once the SPI host issues this command, the SC18IS600/601 will access the I2C-bus slave device and start sending the I2C-bus data bytes. When the I2C-bus write transaction has successfully finished, and interrupt is generated on the INT pin, and the `transaction completed' status can be read in I2CStat. Note that the third byte sent by the host is the device I2C-bus slave address. The SC18IS600/601 will ignore the least significant bit so a write will always be performed even if the least significant bit is a `1'.
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SPI to I2C-bus interface
6.6.2 Read N bytes from I2C-bus slave device
SPI host sends 0x01 COMMAND NUMBER OF BYTES SLAVE ADDRESS +R
CS SCLK
MOSI
command 0x01
number of bytes D[7:0]
slave address A[7:1] 1
002aab719
Fig 14. Read N bytes from I2C-bus slave device
Once the host issues this command, the SC18IS600/601 will start an I2C-bus read transaction on the I2C-bus to the specified slave address. Once the data is received, the SC18IS600/601 will place this data in the receiver buffer, and will generate an interrupt on the INT pin. The `transaction completed' status can be read in the I2CStat. Note that the data is not returned until a Read Buffer command is performed (see Section 6.6.4 "Read buffer"). Note that the third byte sent by the host is the device slave address. The SC18IS600/601 will ignore the least significant bit so a read will always be performed even if the least significant bit is a `0'. The maximum number of bytes to be read is 96.
6.6.3 I2C-bus read after write
SPI host sends NUMBER OF NUMBER OF 0x02 WRITE READ COMMAND BYTES BYTES SLAVE ADDRESS +W DATA WRITE BYTE 0 DATA WRITE BYTE N SLAVE ADDRESS +R
002aab720
Fig 15. I2C-bus read after write
Once the host issues this command, the SC18IS600/601 will start a write transaction on the I2C-bus to the specified slave address. Once the data is written, the SC18IS600/601 will read data from the specified slave, place the data in the Receiver Buffer and generate an interrupt on the INT pin. The `transaction completed' status can be read in I2CStat. Note that the data is not returned until a `Read Buffer' command is performed.
6.6.4 Read buffer
SPI host sends 0x06 COMMAND DATA BYTE 1 DATA BYTE N
002aab868
Fig 16. Read buffer
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SPI to I2C-bus interface
When the host issues a Read Buffer command, the SC18IS600/601 will return the data in the Read Buffer on the MISO pin. Note that the Read Buffer will be overwritten if an additional `Read N bytes' or a `Read after write' command is executed before the Read Buffer command.
6.6.5 I2C-bus write after write
SPI host sends 0x03 NUMBER OF NUMBER OF COMMAND BYTES 1 BYTES 2 SLAVE 1 ADDRESS + W DATA BYTE 1 DATA BYTE N SLAVE 2 ADDRESS + W DATA BYTE 1 DATA BYTE N
002aab721
Fig 17. Write after write
When the host issues this command, the SC18IS600/601 will first write N data bytes to the I2C-bus slave 1 device followed by a write of M data bytes to the I2C-bus slave 2 device.
6.6.6 SPI configuration
SPI host sends 0x18 COMMAND SPI CONFIGURATION
CS SCLK
MOSI
character 0x18
SPI configuration data
002aab722
Fig 18. SPI configuration Table 9. 0x81 0x42 SPI configuration Data order LSB first MSB first (default)
SPI configuration
The SPI configuration command can be used to change the order in which the bits of SPI data byte are sent on the SPI bus. In the LSB first configuration (SPI configuration data is 0x81), bit 0 is the first bit sent of any SPI byte. In MSB first (SPI configuration data is 0x42), bit 7 is the first bit sent. Table 9 shows the two possible configurations that can be programmed.
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SPI to I2C-bus interface
6.6.7 Write to SC18IS600/601 internal registers
SPI host sends 0x20 COMMAND REGISTER X DATA BYTE
CS SCLK
MOSI
character 0x20
register X
data byte
002aab723
Fig 19. Write to SC18IS600/601 internal registers
A Write Register function is initiated by sending a 0x20 command followed by an internal register address to be written (see Section 6.1). The register data byte follows the register address. Only one register can be accessed in a single transaction. There is no auto-incrementing of the register address.
6.6.8 Read from SC18IS600/601 internal register
SPI host sends 0x21 COMMAND REGISTER X REGISTER DATA
CS SCLK
MOSI
character 0x21
register X
dummy byte
MISO
data byte
002aab724
Fig 20. Read from SC18IS600/601 internal register
A Read Register function is initiated by sending a 0x21 command followed by an internal register address to be read (see Section 6.1) and a dummy byte. The data byte of the read register is returned by the SC18IS600 on the MISO pin. Only one register can be accessed in a single transaction. There is no auto-incrementing of the register address. Note that write and read from internal registers are processed immediately as soon as the SC18IS600/601 determines the intended register.
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SPI to I2C-bus interface
6.6.9 Power-down mode
SPI host sends 0x30 COMMAND 0x5A 0xA5
CS SCLK
MOSI
character 0x30
character 0x5A
character 0xA5
002aab725
Fig 21. Power-down mode
The SC18IS600/601 can be placed in a low-power mode where the internal oscillator is stopped and it will no longer respond to SPI messages. Enter the Power-down mode by sending the power-down command (0x30) followed by the two defined bytes, which are 0x5A followed by 0xA5. If the exact message is not received, the device will not enter the power-down state. Before entering the power-down state, WAKEUP/IO4 should be placed in a HIGH state. To exit the power-down state, the WAKEUP/IO4 should be brought LOW. After leaving the power-down state, the WAKEUP/IO4 can once again be used as a general-purpose IO pin.
7. Limiting values
Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2] Symbol Tamb(bias) Tstg Vn IOH(I/O) IOL(I/O) II/O(tot)(max) Ptot/pack
[1] [2] [3]
Parameter bias ambient temperature storage temperature voltage on any other pin HIGH-level output current per input/output pin LOW-level output current per input/output pin maximum total I/O current total power dissipation per package
Conditions operating referenced to VSS
Min -55 -65 -0.5 [3]
Max +125 +150 +5.5 8 20 120 1.5
Unit C C V mA mA mA W
-
This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. Parameters are valid over the operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Based on package heat transfer, not device power consumption.
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8. Static characteristics
Table 11. Static characteristics VDD = 2.4 V to 3.6 V; Tamb = -40 C to +85 C (industrial); unless otherwise specified. Symbol IDD(oper) IDD(idle) IDD(tpd) Vth(HL) Vth(LH) Vhys VOL Parameter operating supply current Idle mode supply current total Power-down mode supply current HIGH-LOW threshold voltage LOW-HIGH threshold voltage hysteresis voltage LOW-level output voltage all pins; IOL = 20 mA all pins; IOL = 10 mA all pins; IOL = 3.2 mA VOH HIGH-level output voltage all pins; IOH = -8 mA; push-pull mode all pins; IOH = -3.2 mA; push-pull mode all pins; IOH = -20 A; quasi-bidirectional mode Cig IIL ILI ITHL RRESET_N(int) input capacitance at gate LOW-level input current input leakage current HIGH-LOW transition current internal pull-up resistance on pin RESET logical 0; VI = 0.4 V all ports; VI = VIL or VIH all ports; logical 1-to-0; VI = 2.0 V at VDD = 3.6 V
[2] [3] [4] [5][6]
Conditions VDD = 3.6 V; f = 12 MHz VDD = 3.6 V; f = 18 MHz VDD = 3.6 V; f = 12 MHz VDD = 3.6 V; f = 18 MHz VDD = 3.6 V; industrial VDD = 3.6 V; extended Schmitt trigger input Schmitt trigger input
Min 0.22VDD VDD - 1
Typ[1] 7 11 3.6 4 < 0.1 0.4VDD 0.6VDD 0.2VDD 0.6 0.3 0.2 -
Max 13 16 4.8 6 5 50 0.7VDD 1.0 0.5 0.3 -
Unit mA mA mA mA A A V V V V V V V V V pF A A A k
VDD - 0.7 VDD - 0.4 VDD - 0.3 VDD - 0.2 -30 10 15 -80 10 -450 30
[1] [2] [3] [4] [5] [6]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. Pin capacitance is characterized but not tested. Measured with pins in quasi-bidirectional mode. Measured with pins in high-impedance mode. Pins in quasi-bidirectional mode with weak pull-up (applies to all pins with pull-ups). Pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V.
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9. Dynamic characteristics
Table 12. Dynamic characteristics VDD = 2.4 V to 3.6 V; Tamb = -40 C to +85 C (industrial); unless otherwise specified.[1] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions SC18IS600; nominal f = 7.3728 MHz; trimmed to 1 % at Tamb = 25 C VDD = 2.4 V to 3.6 V Variable clock Min 7.189 Max 7.557 fosc = 12 MHz Unit Min 7.189 Max 7.557 MHz
External clock input (SC18IS601); see Figure 23 fosc TCLCL tCHCX tCLCX tCLCH tCHCL tgr tsa oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time glitch rejection time signal acceptance time RESET pin any pin except RESET RESET pin any pin except RESET SPI slave interface fSPI TSPICYC tSPILEAD tSPILAG tSCLKH tSCLKL tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV tSPIOH tSPIR SPI operating frequency 2.0 MHz SPI cycle time SPI enable lead time SPI enable lag time SCLK HIGH time SCLK LOW time SPI data set-up time SPI data hold time SPI access time SPI disable time SPI enable to output data valid time SPI output data hold time SPI rise time SPI outputs (SCLK, MOSI, MISO) SPI inputs (SCLK, MOSI, MISO, CS) tSPIF SPI fall time SPI outputs (SCLK, MOSI, MISO) SPI inputs (SCLK, MOSI, MISO, CS)
[1] [2]
[2] [2]
0 83 22 22 125 50 0
6 fosc
12 TCLCL - tCLCX TCLCL - tCHCX 8 8 50 15 fosc 6
22 22 125 50 0 500 4 4 190 190 100 100 0 0 -
8 8 50 15 2.0 120 240 240 167 100 2000 100 2000
MHz ns ns ns ns ns ns ns ns ns MHz ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns
Glitch filter
2.0 MHz 2.0 MHz
120 240 240 167 100 2000 100 2000
4 4
3 fosc 3 fosc
100 100 0 2.0 MHz 2.0 MHz 3.0 MHz 0 0 0 0 -
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. SCL and SDA do not have glitch suppression circuits.
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SPI to I2C-bus interface
Table 13. Dynamic characteristics VDD = 3.0 V to 3.6 V; Tamb = -40 C to +85 C (industrial); unless otherwise specified.[1] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions SC18IS600; nominal f = 7.3728 MHz; trimmed to 1 % at Tamb = 25 C Variable clock Min 7.189 Max 7.557 fosc = 18 MHz Min 7.189 Max 7.557 MHz Unit
External clock input (SC18IS601); see Figure 23 fosc TCLCL tCHCX tCLCX tCLCH tCHCL tgr tsa oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time glitch rejection time signal acceptance time RESET pin any pin except RESET RESET pin any pin except RESET SPI slave interface fSPI TSPICYC tSPILEAD tSPILAG tSCLKH tSCLKL tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV tSPIOH tSPIR SPI operating frequency SPI cycle time SPI enable lead time SPI enable lag time SCLK HIGH time SCLK LOW time SPI data set-up time SPI data hold time SPI access time SPI disable time SPI enable to output data valid time SPI output data hold time SPI rise time SPI outputs (SCLK, MOSI, MISO) SPI inputs (SCLK, MOSI, MISO, CS) tSPIF SPI fall time SPI outputs (SCLK, MOSI, MISO) SPI inputs (SCLK, MOSI, MISO, CS)
[1] [2]
[2] [2]
0 55 22 22 125 50 0
6 fosc
18 TCLCL - tCLCX TCLCL - tCHCX 5 5 50 15 fosc
22 22 125 50 0 333 4 4 167 167 100 100 0 0 -
5 5 50 15 3 80 160 160 100 2000 100 2000
MHz ns ns ns ns ns ns ns ns ns MHz ns s s ns ns ns ns ns ns ns ns ns ns ns ns
Glitch filter
3.0 MHz 3.0 MHz 3.0 MHz 3.0 MHz
3 3
6
80 160 160 100 2000 100 2000
4 4
fosc fosc
100 100 0 3.0 MHz 3.0 MHz 0 0 0 -
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. SCL and SDA do not have glitch suppression circuits.
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CS tSPIF tSPILEAD tSPIF SCLK (input) tSPIOH tSPIDV tSPIA MISO (output) not defined MOSI (input) slave MSB/LSB out tSPIDSU tSPIDH tSPIDSU slave LSB/MSB out tSPIDSU tSPIDH tSPIOH tSPIDV tSPIOH tSPIDV tSPIDIS tSCLKL tSCLKH tSPIR tSPILAG TCLCL tSPIR
MSB/LSB in
LSB/MSB in
002aab797
Fig 22. SPI slave timing (Mode 3)
VDD - 0.5 V 0.45 V
0.2VDD + 0.9 V 0.2VDD - 0.1 V tCHCX tCHCL tCLCX TCLCL tCLCH
002aab886
Fig 23. External clock timing
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Table 14. Symbol tSPICLKW tCSW tSPILAG1 td
Additional SPI AC characteristics Parameter SPICLK HIGH time CS HIGH time SPI enable lag time 1 delay time Conditions between two SPI bytes between two SPI transactions in a SPI to I2C-bus transaction from last SCLK pulse to SDA LOW in a SPI to transaction I2C-bus Min 8 Typ Max Unit s s s s
refer to Figure 25 refer to Figure 26 refer to Figure 27
tSPICLKW SCLK tSPILEAD CS tCSW SDA
002aab927
tSPILAG1
td
Fig 24. SPI to I2C-bus timing diagram
8 tCSW (s) 6
002aab929
5 tSPILAG1 (s) 4
002aab930
3 4 2 2
1
0 1.843 3.687 7.373 12.00 18.00 CLKIN frequency (MHz)
0 1.843 3.687 7.373 12.00 18.00 CLKIN frequency (MHz)
Fig 25. tCSW as a function of CLKIN frequency
160 td (s) 120
Fig 26. tSPILAG1 as a function of CLKIN frequency
002aab931
80
40
0 1.843 3.687 7.373 12.00 18.00 CLKIN frequency (MHz)
Fig 27. td as a function of CLKIN frequency
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10. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 28. Package outline SOT403-1 (TSSOP16)
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SPI to I2C-bus interface
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
SOT616-3
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 y1 C y
e 7 L 6
e
Eh
1/2 e
e2
1 18 terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.75 2.45 E (1) 4.1 3.9 Eh 2.75 2.45 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-3 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-11-19 05-03-10
Fig 29. Package outline SOT616-3 (HVQFN24)
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11. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
11.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
11.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
11.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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SPI to I2C-bus interface
11.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 15 and 16
Table 15. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 16. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 30. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
12. Abbreviations
Table 17. Acronym ASCII CPU GPIO I/O I2C-bus LSB MSB PCB SPI UART Abbreviations Description American Standard Code for Information Interchange Central Processing Unit General Purpose Input/Output Input/Output Inter-Integrated Circuit bus Least Significant Bit Most Significant Bit Printed-Circuit Board Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter
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13. Revision history
Table 18. Revision history Release date 20080728 Data sheet status Product data sheet Change notice Supersedes SC18IS600_601_4 Document ID SC18IS600_601_5 Modifications:
*
Table 9 "SPI configuration": - SPI configuration for LSB first data order changed from "0x42" to "0x81" - SPI configuration for MSB first data order changed from "0x81" to "0x42"
*
Section 6.6.6 "SPI configuration", first paragraph: - 2nd sentence: changed from "0x42" to "0x81" - 3rd sentence: changed from "0x81" to "0x42"
SC18IS600_601_4 SC18IS600_601_3 SC18IS600_601_2 SC18IS600_601_1
20080320 20061213 20060811 20060224
Product data sheet Product data sheet Product data sheet Product data sheet
-
SC18IS600_601_3 SC18IS600_601_2 SC18IS600_601_1 -
SC18IS600_601_5
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14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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16. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 7 8 9 10 11 11.1 11.2 11.3 11.4 12 13 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 6 Register descriptions . . . . . . . . . . . . . . . . . . . . 6 Programmable IO port configuration register (IOConfig) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Quasi-bidirectional output configuration . . . . . . 7 Open-drain output configuration . . . . . . . . . . . . 8 Input-only configuration . . . . . . . . . . . . . . . . . . 8 Push-pull output configuration . . . . . . . . . . . . . 8 I/O pins state register (IOState) . . . . . . . . . . . . 9 I2C-bus address register (I2CAdr) . . . . . . . . . . 9 I2C-bus clock rates register (I2CClk) . . . . . . . . 9 I2C-bus time-out register (I2CTO) . . . . . . . . . . 10 I2C-bus status register (I2CStat). . . . . . . . . . . 11 External clock input (SC18IS601). . . . . . . . . . 12 I2C-bus serial interface . . . . . . . . . . . . . . . . . . 12 Serial Peripheral Interface (SPI) . . . . . . . . . . . 12 SPI message format . . . . . . . . . . . . . . . . . . . . 13 Write N bytes to I2C-bus slave device. . . . . . . 13 Read N bytes from I2C-bus slave device . . . . 14 I2C-bus read after write. . . . . . . . . . . . . . . . . . 14 Read buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C-bus write after write . . . . . . . . . . . . . . . . . 15 SPI configuration . . . . . . . . . . . . . . . . . . . . . . 15 Write to SC18IS600/601 internal registers . . . 16 Read from SC18IS600/601 internal register. . 16 Power-down mode . . . . . . . . . . . . . . . . . . . . . 17 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 Static characteristics. . . . . . . . . . . . . . . . . . . . 18 Dynamic characteristics . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering of SMD packages . . . . . . . . . . . . . . 25 Introduction to soldering . . . . . . . . . . . . . . . . . 25 Wave and reflow soldering . . . . . . . . . . . . . . . 25 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 14 14.1 14.2 14.3 14.4 15 16 Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 29 29 29 29 29 30
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
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For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 July 2008 Document identifier: SC18IS600_601_5

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